The present invention relates to a method for optimized buffer placement based on timing and capacitance assertions in a functional chip unit comprising a signal source and multiple macros, each having a sink, whereby the placement of the source and the macros with the sinks is pre-designed and the buffers are placed in branches connecting the source with the multiple sinks. The invention further relates to a computer-readable medium containing a set of instructions that causes a computer to perform the above method and a computer program product comprising a computer-usable medium including a computer-usable program code, wherein the computer-usable program code is adapted to execute the above method. The invention also relates to a system for optimized buffer placement based on timing and capacitance assertions in a functional chip unit comprising a single source and multiple macros each having a sink, the system comprising a processing unit with a storage device for storing a computer-usable program code and a processor for executing the computer-usable program code for optimizing buffer placement according to the above method.
The placement of buffers in signal paths is an important issue when designing a functional chip unit. The term functional chip unit refers to any functional entity on a chip, or to the entire chip itself. Important is, that the chip unit comprises individual macros, which have to be connected to the source. The signal paths have to be designed, so that signals are transmitted between the source and the different sinks under consideration of required arrival time (RAT), and having a sufficient slew, so that the signal can be correctly identified upon reception. Buffers, which are inserted in the signal paths, usually consist of a group of two inverters and refresh the signal along the signal path. The drawback of the buffers is a negative impact on the arrival time of the signal.
It is therefore important to properly design the branches between the source and the sinks. In the state of the art, this is done by timing runs based on assertions of macros or instances and I/O-nets, where the term instances refers to any kind of functional groups within the functional chip unit. The provided placement of the source and the macros with the sinks as predesigned is loaded into a router, which provides routing for all branches within the given chip unit. All instances are utilized with data from the timing run and a buffer optimization tool adds buffers within the branches. Then, a next timing run based on the routing with the added buffers is performed, which usually identifies timing problems in at least some of the branches. Problems considered here are a signal slack, which refers to the time the signal requires for being transmitted between the source and the sink, and slew problems. These problems are based on non-optimal buffer placement. Accordingly, branches with timing problems have to be re-designed manually, comprising re-routing the branch and replacing the buffers. Then a new timing run has to be performed and the subsequent steps as described above have to be executed in an iterative way, until the functional chip unit fulfils all slack and slew requirements. This method is very time-consuming and not deterministic, so that an improvement is desired.